eWLB

Embedded Wafer Level Ball Grid Array

The Market Leader in eWLB Technology

STATS ChipPAC is at the forefront of eWLB innovation:
  • First to achieve high volume eWLB manufacturing with best-in-class yields
  • First to implement 300mm eWLB reconstituted wafer manufacturing technology
  • Pioneering the development of next-generation eWLB with technology partners

    As the world demand for portable electronics has accelerated, the need to make semiconductors smaller, faster, lighter and cheaper has never been greater. Consumers have made it clear that they are looking for portable devices that have the most features and functionality in the smallest size possible and at a price they are willing to pay. At STATS ChipPAC, we offer advanced, leading edge manufacturing and testing solutions for mobile applications with embedded Wafer-Level Ball Grid Array, or eWLB, technology.

    Embedded Wafer Level Ball Grid Array (eWLB) technology was developed to provide a wafer level packaging solution for semiconductor devices requiring a higher integration level and a greater number of external contacts. eWLB technology uses a combination of traditional ‘front-end’ and ‘back-end’ semiconductor manufacturing techniques which greatly reduces manufacturing costs while providing a smaller package footprint with higher input / output (I/O) along with increased thermal and electrical performance. eWLB technology is an enhancement of standard wafer level packages (WLPs) and is successfully enabling semiconductor manufacturers to provide the smallest possible, highest performing semiconductor package technology. In addition, no bumping is required as the package is essentially built on top of a reconstituted wafer.  

    High Volume eWLB Manufacturing with Best-in-Class Yields

    Backed by a strong infrastructure and cost effective manufacturing process, STATS ChipPAC offers a high performance solution at a lower cost point with volume and maturity, leveraging the potential of batch panel processing of high density wafer fabrication redistribution technology. STATS ChipPAC has established a robust eWLB high volume manufacturing process with automated wafer reconstitution (including wafer level molding), redistribution using thin film technology, solder ball mount, package singulation and testing.

    300mm Manufacturing

    Incoming wafers in both 200mm and 300mm diameters can be supported.  STATS ChipPAC is the first in the world to implement 300mm eWLB manufacturing.  300mm is the most cost effective eWLB packaging solution in the market, offering high performance at a lower cost.  Transition to 300mm reconstituted wafers increases capacity and provides significant cost advantages to customers by providing higher efficiency and increasing economy of scale.

    eWLB Features

    eWLB is a Fan-Out WLP (FO-WLP) as opposed to a more conventional Fan-In WLP (FI-WLP). The advantage is that the eWLB package size is decoupled from the die size, unlike FI-WLP, and ball pitch and I/O count is not limited by die size.

    Thus, die shrinks can be accommodated and larger ball pitches that would not fit within the die area of a FI-WLP can be supported. Due to use of special materials, the package size and ball count of eWLB can be extended beyond that of FI-WLP and still meet board level reliability requirements. This allows for a broader application range for the eWLB to larger size and ball count mobile and consumer devices, while still giving the advantages of WLP related to performance, simple logistics and supply chain, lead free/halogen free and compatibility with advanced wafer fabrication nodes.

    eWLB technology provides significant cost and size benefits, compared to other technology available today:

    • Combines traditional front-end and back-end manufacturing techniques with parallel processing of all chips on the wafer
    • Batch processing increases throughput and reduces manufacturing costs
    • Elimination of substrate simplifies supply chain and reduces cost
    • Provides the performance of fan-in WLP but decouples die from package size for greater flexibility
    • Enables a dramatically higher number of external contacts as compared to fan-in WLP
    • 1 and 2 sided PoP versions with total height less than 1.0mm
    • MCP versions with IPD integration capability
    • Integration of TSV and IPD into eWLB delivers increased performance, design flexibility and smaller form factor
    • No substrate required resulting in a thinner package with lower warpage
    • Unique structure allows thinnest advanced package profile and excellent 2D and 3D integration platform
    • Miniaturized high performance package
    • Green packaging (Pb-free and Halogen-free)
    • Cu/low-k (ELK) compatible packaging technology
    • Batch process of wafer level including wafer-level test
    • Embeds die in mold during assembly/packaging
    • Supports incoming wafers in both 200mm and 300mm diameters
    • No bumping required
    • Low packaging and test costs due to batch process
    • Excellent electrical and thermal performance
    • Simple logistics and supply chain (no substrate, bumping, etc.)

    Applications

    eWLB is uniquely suited to a wide and growing range of applications including baseband, RF, power management, analog and other emerging applications for mobile, connectivity, MCU, networking and consumer applications.

    Next Generation eWLB

    • Ultra thin package profile: 2D down to 0.5mm; 2.5D down to 0.8mm; 3D down to 0.8mm
    • Scalable heterogeneous integration
    • Ultra fine pitch and maximum I/O density
    • Low cost solutions
    • Excellent electrical & thermal performance
    • High bandwidth wide I/O 3D incorporating TSV

    The next generation of eWLB technology leverages the success of first-generation eWLB (single metal RDL on the bottom side of the eWLB package), with focused development on multi-metal layer RDL, multiple die side-by-side (greater than 2), extension of package size to less than 2x2mm and greater than 14x14mm, reduction of package thickness to less than 0.5mm and smaller (including leadless land grid array version), RLC-IPD, heterogenous integration and eWLB-PoP technologies. eWLB is also ideally suited to 3D applications such as SiP and other 3D configurations using STATS ChipPAC’s TSV technology. In addition, STATS ChipPAC is actively working with technology partners to further extend eWLB capabilities to meet the needs of a broader set of advanced applications.

    eWLB Process Flow

    eWLB manufacturing is distinguished by an innovative process where an artificial wafer is created by embedding pre-diced silicon chips onto a blank metal carrier.
    1) Reconstituted wafer

    • Wafer saw and pick-and-place from incoming wafer
    • Probed good die
    • Molded reconstituted wafer using proven materials
    • Molded artificial wafer starting point for thin film technology
    2) Redistribution
    • Thin film technology with advanced design rules
    • Standard thin film equipment
    • Proven and reliable material set
    3) Ball Mount and Singulation
    • Standard back-end assembly flow (and equipment)
    4) Test, Mark, Scan, Pack
    • Standard or wafer level-based test flow
    • Standard assembly

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